1. Field of the Invention
The present invention relates to processors, and more particularly to sampling mechanisms of processors.
2. Description of the Related Art
One method of understanding the behavior of a program executing on a processor is for a processor to randomly sample instructions as the instructions flow through the instruction pipeline. For each sample, the processor gathers information about the execution history and provides this information to a software performance monitoring tool. Unlike tools which aggregate information over many instructions (e.g., performance counters), such an instruction sampling mechanism allows the performance analyst to map processor behaviors back to a specific instruction.
In a multi-threaded processor, the processor's architectural state is replicated for each thread. For example, each thread has its own copy of the general purpose registers. This leads to much replication of state, at commensurate implementation cost.